Home  Catalogue of authors Catalogue of works Full search Add papers Login

Computing observability of gates in combinational logic circuits by bit-parallel simulation
Authors
 Telpukhov D.V.
 Nadolenko V.V.
 Gurov S.I.
Date of publication
 2019
Type of work
 статья в научном журнале
Library reference
 Telpukhov D.V., Nadolenko V.V., Gurov S.I. Computing observability of gates in combinational logic circuits by bit-parallel simulation. Computational Mathematics and Modeling. 2019. Т. 30. № 2. С. 177-190. doi.org/10.1007/s10598-019-09445-y (Scopus)
To IPPM site    To InfoMES site    Feedback
Copyright © 2012-2024 IPPM RAS. All Rights Reserved.
Updated and substantially revised version of system of 2016.
Design of site: IPPM RAS