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The Analysis of Logic Resynthesis Methods to Increase the Fault Tolerance of Combinational Circuits for Single Failures
Authors
 Vasilyev N.O.
 Zapletina M.A.
 Ivanova G.A.
Date of publication
 2021
Type of work
 текст доклада на конференции
Library reference
 Vasilyev N.O., Zapletina M.A., Ivanova G.A. The Analysis of Logic Resynthesis Methods to Increase the Fault Tolerance of Combinational Circuits for Single Failures. 2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus). 2021. Pp. 2050-2053. doi: 10.1109/ElConRus51938.2021.9396456.
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