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Rajendran Panda
1997
Gavrilov S.V., Glebov A.L., Pullela S., Moore S., Vijayan G., Dharchoudhury A., Rajendran Panda, Blaauw D.
Library-Less Synthesis for Static CMOS Combinational Logic Circuits
2006
Gavrilov S.V., Glebov A.L., Sundareswaran Savithri, Rajendran Panda
Accurate Input Slew and Input Capacitance Variations for Statistical Timing Analysis
2008
Sundareswaran Savithri, Gavrilov S.V., Soloviev Roman, Rajendran Panda
A Timing Methodology Considering Within-Die Clock Skew Variations
Gavrilov S.V., Soloviev Roman, Sundareswaran Savithri, Rajendran Panda
Interdependent setup-hold characterization and timing analysis
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